A NAND-type flash memory is widespread as a storage device for a large volume of data. At present, memory cells are miniaturized for cost reduction and capacity increase per bit. Further miniaturization in the future is demanded. However, further miniaturization of the flash memory involves many problems to be solved, such as the development of lithography technology, a short channel effect, inter-element interference, and the inhibition of inter-element variations. Therefore, there is a strong possibility that future continuous improvement of storage density only by the development of simple in-plane miniaturization technology is difficult.
Accordingly, in order to raise the degree of memory cell integration, there has recently been suggested a three-dimensional stacked layer type semiconductor memory in which memory cells are three-dimensionally arranged.
In the conventional flash memories, drain ends of active areas (semiconductor layers) that are stacked are isolated from each other by an insulating layer, and one drain-side select transistor is provided for the active areas. Drain electrodes (contact plugs) are independently connected to the active areas, respectively.
However, in this structure, the drain electrode is formed for each memory string (active area), and regions to form the drain electrodes are therefore needed. As a result, increasing the number of memory strings to be stacked is not a great contribution to the improvement in the degree of memory cell integration because the regions to form the drain electrodes increase proportionately.
Another problem is that one bit line is connected to one memory string via the drain electrode so that the number of bit lines arranged on a memory cell array increases and their layout is complicated.
In view of such circumstances, there has been suggested a technique to connect drain ends of stacked active areas by a common semiconductor layer and provide drain-side select transistors (layer select transistors) for the active areas (e.g., refer to FIG. 13 in PCT/JP2009/060803).
According to this technique, one common drain electrode (contact plug) has only to be connected to memory strings (active areas). Therefore, the degree of memory cell integration can be improved by increasing the number of memory strings to be stacked.
However, intensive studies by the present inventors have proved that sufficient cut-off characteristics for the drain-side select transistors (layer select transistors) cannot be obtained by the device structure disclosed in the prior application). That is, when a current is passed through one selected memory string, unnecessary currents are also passed through the remaining unselected memory strings. This prevents accurate reading/writing/erasing.